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Proceedings Paper

Process improvements of applying 193-nm lithography to 90-nm logic implant layer
Author(s): D.C. OweYang; Harrison Chen; R.M. Deng; Bang-Ching Ho
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Paper Abstract

Controlling critical dimension (CD) uniformity and overlay accuracy are crucial to achieving quality lithography. The continuous reduction in minimum feature and unit cell sizes on semiconductor wafers has posed significant strain to lithography engineers. According to the 2001 ITRS roadmap, the half pitch of DRAM will be 100 nm and the overlay requirement will be 35 nm for the Poly layer in 2003. Up to date, the 193 nm lithography is mainly applied to those critical layers, such as Poly, Contact, Metal and Via in chip process flow. For the non-criticals, such as well and source-drain implant layers, we still use 248 nm or even 365 nm lithography. Such a situation poses potential challenges when we try to improve the overlay accuracy demanded by area reduction on unit cells since a mix-and-match between 193 nm and 248 nm has to be carried out. In the 90 nm logic process, the overlay requirement of implant layer to critical layers are tightened to 60 nm, which has been close to the current limit of tool matching capability between 193 nm and 248 nm. Stimulated by such an issue we start to implement 193 nm lithography into implant layers. In this paper, a full lithographic process characterization for 90 nm logic implant layers using 193 nm lithography is reported. The photo resist swing cure was first generated to determine the resist thickness. A top antireflective coating (ARC) was also applied to reduce the photo resist swing effect. After the target thickness of photo resist is being defined, three different thickness of resist was coated including targeted, thinner and thicker than targeted. Resist coated wafers were through bombardment of implantation species, then were sent to SIMS analysis. Based on the SIMS results, the target thickness is verified to be safe for the high voltage implantation required by process flow. The DOF data were collected for six kinds of patterns. The proximity effect data of 193 nm is only half of that resulted in 248 nm lithography. So, the optical proximity correction (OPC) may not be needed if 193 nm lithography is used. Besides, the CD variation is also improved when compared to the 248 nm lithography, especially when resist patterns are printed on topographic wafers. As the chip continues its shrinkage, the 193 nm lithography will be a must for implant layers at some point.

Paper Details

Date Published: 2 June 2003
PDF: 12 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.483691
Show Author Affiliations
D.C. OweYang, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Harrison Chen, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
R.M. Deng, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)
Bang-Ching Ho, Taiwan Semiconductor Manufacturing Co., Ltd. (Taiwan)

Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)

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