The increasing of wafer size from 200mm to 300mm and downscaling of IC design rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment and overlay measurement. In this paper, we present a concept of total process control of alignment and overlay, which we had used to get deeper understanding of our metal process with W-CMP and aluminum sputter. Traditionally, a lot of works are focusing on alignment process control and overlay process control separately. However, based on what we had observed, the final overlay performance is largely affected by the difference between alignment system (alignment mark, alignment sensor and process) and overlay system (overlay mark, overlay sensor and process). Deeper understanding of this difference between alignment and overlay system do help us to get better overlay process control o and process/tool matching.

Date Published: 2 June 2003
PDF: 12 pages
Proc. SPIE 5038, Metrology, Inspection, and Process Control for Microlithography XVII, (2 June 2003); doi: 10.1117/12.482651

Published in SPIE Proceedings Vol. 5038:
Metrology, Inspection, and Process Control for Microlithography XVII
Daniel J. Herr, Editor(s)