Share Email Print

Proceedings Paper

Lithography strategy for 65-nm node
Author(s): Yan A. Borodovsky; Richard E. Schenker; Gary A. Allen; Edita Tejnil; David H. Hwang; Fu-Chang Lo; Vivek K. Singh; Robert E. Gleason; Joseph E. Brandenburg; Robert M. Bigwood
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Intel will start high volume manufacturing (HVM) of the 65nm node in 2005. Microprocessor density and performance trends will continue to follow Moore's law and cost-effective patterning solutions capable of supporting it have to be found, demonstrated and developed during 2002-2004. Given the uncertainty regarding the readiness and respective capabilities of 157nm and 193nm lithography to support 65nm technology requirements, Intel is developing both lithographic options and corresponding infrastructure with the intent to use both options in manufacturing. Development and use of dual lithographic options for a given technology node in manufacturing is not a new paradigm for Intel: whenever introduction of a new exposure wavelength presented excessive risk to the manufacturing schedule, Intel developed parallel patterning approaches in time for the manufacturing ramp. Both I-line and 248nm patterning solutions were developed and successfully used in manufacturing of the 350nm node at Intel. Similarly, 248nm and 193nm patterning solutions were fully developed for 130nm node high volume manufacturing.

Paper Details

Date Published: 1 August 2002
PDF: 14 pages
Proc. SPIE 4754, Photomask and Next-Generation Lithography Mask Technology IX, (1 August 2002); doi: 10.1117/12.476916
Show Author Affiliations
Yan A. Borodovsky, Intel Corp. (United States)
Richard E. Schenker, Intel Corp. (United States)
Gary A. Allen, Intel Corp. (United States)
Edita Tejnil, Intel Corp. (United States)
David H. Hwang, Intel Corp. (United States)
Fu-Chang Lo, Intel Corp. (United States)
Vivek K. Singh, Intel Corp. (United States)
Robert E. Gleason, Intel Corp. (United States)
Joseph E. Brandenburg, Intel Corp. (United States)
Robert M. Bigwood, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 4754:
Photomask and Next-Generation Lithography Mask Technology IX
Hiroichi Kawahira, Editor(s)

© SPIE. Terms of Use
Back to Top