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Proceedings Paper

Mapping of H.264 decoding on a multiprocessor architecture
Author(s): Erik B. van der Tol; Egbert G.T. Jaspers; Rob H. Gelderblom
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Paper Abstract

Due to the increasing significance of development costs in the competitive domain of high-volume consumer electronics, generic solutions are required to enable reuse of the design effort and to increase the potential market volume. As a result from this, Systems-on-Chip (SoCs) contain a growing amount of fully programmable media processing devices as opposed to application-specific systems, which offered the most attractive solutions due to a high performance density. The following motivates this trend. First, SoCs are increasingly dominated by their communication infrastructure and embedded memory, thereby making the cost of the functional units less significant. Moreover, the continuously growing design costs require generic solutions that can be applied over a broad product range. Hence, powerful programmable SoCs are becoming increasingly attractive. However, to enable power-efficient designs, that are also scalable over the advancing VLSI technology, parallelism should be fully exploited. Both task-level and instruction-level parallelism can be provided by means of e.g. a VLIW multiprocessor architecture. To provide the above-mentioned scalability, we propose to partition the data over the processors, instead of traditional functional partitioning. An advantage of this approach is the inherent locality of data, which is extremely important for communication-efficient software implementations. Consequently, a software implementation is discussed, enabling e.g. SD resolution H.264 decoding with a two-processor architecture, whereas High-Definition (HD) decoding can be achieved with an eight-processor system, executing the same software. Experimental results show that the data communication considerably reduces up to 65% directly improving the overall performance. Apart from considerable improvement in memory bandwidth, this novel concept of partitioning offers a natural approach for optimally balancing the load of all processors, thereby further improving the overall speedup.

Paper Details

Date Published: 7 May 2003
PDF: 12 pages
Proc. SPIE 5022, Image and Video Communications and Processing 2003, (7 May 2003); doi: 10.1117/12.476234
Show Author Affiliations
Erik B. van der Tol, Philips Research Labs. (Netherlands)
Egbert G.T. Jaspers, Philips Research Labs. (Netherlands)
Rob H. Gelderblom, Philips Research Labs. (Netherlands)

Published in SPIE Proceedings Vol. 5022:
Image and Video Communications and Processing 2003
Bhaskaran Vasudev; T. Russell Hsing; Andrew G. Tescher; Touradj Ebrahimi, Editor(s)

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