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Proceedings Paper

Error budget for a 193-nm complementary phase-shift mask
Author(s): Nicholas K. Eib; Olga Kobozeva; Chris Neville; Ebo H. Croffie
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Paper Abstract

We have been exploring alternating aperture phase-shifting masks for Application Specific Integrated Circuit poly gate CD's below 100 nm. The implementation is dark field altPSM with a complementary bright field binary 'trim' mask. The alternating phase shift approach is attractive because of the potential for improved resolution, increased individual process windows, and reduced developed resist line edge roughening (LER) needed for superior device performance. This can be accomplished with moderately low exposure tool numerical aperture (NA). However, these improvements must justify the increased mask cost, throughput reduction of dual mask, and the necessity of optical and process pattern correction (OPC) of 2 masks. Compared to the single reticle non-strong phase shift approach, the altPSM option potentially has new modes of failure: image intensity imbalance between the 0 and 180 degree phases, phase error sensitivity, and quartz sidewall angle sensitivity, all as a function of feature p9itch. Additionally, the high coherence required to print altPSM sensitivities plus corrections for mask writing inaccuracies, lithography printing inaccuracies, and etch inhomogeneities. Manufacturing with altPSM adds additional CD uniformity requirements across the chip. In this paper we discuss the performance of a 193 nm altPSM dual mask set's printing across the exposure slit of an ASML/950 scanner in the 80 nm regime. We will show how wafer level image placement error varies with focus and pitch across the scanner slit. We will discuss 3 methods of OPC correction as a function of CD and pitch across the scanner slit, their self-agreement, and OPC grid requirements. We will also present OPC corrected common process windows across the slit.

Paper Details

Date Published: 12 July 2002
PDF: 11 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475694
Show Author Affiliations
Nicholas K. Eib, LSI Logic Corp. (United States)
Olga Kobozeva, LSI Logic Corp. (United States)
Chris Neville, LSI Logic Corp. (United States)
Ebo H. Croffie, LSI Logic Corp. (United States)

Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Alexander Starikov; Kenneth W. Tobin Jr., Editor(s)

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