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Proceedings Paper

Investigation of the physical and practical limits of dense-only phase-shift lithography for circuit feature definition
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Paper Abstract

The rise of low-k1 optical lithography in IC manufacturing has introduced new questions concerning the physical and practical limits of particular sub-wavelength resoltuion-enhanced imaging approaches. For a given application tradeoffs between mask complexity design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only PSM approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1 < 0.3, thus enabling 90-nm node lithography with high-NA 248 nm exposure systems. We presents the results of experiments, simulations, and analysis designed to explore the tradeoffs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.

Paper Details

Date Published: 12 July 2002
PDF: 14 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475686
Show Author Affiliations
Brian Tyrrell, MIT Lincoln Lab. (United States)
Michael Fritze, MIT Lincoln Lab. (United States)
Renee D. Mallen, MIT Lincoln Lab. (United States)
Bruce Wheeler, MIT Lincoln Lab. (United States)
Peter D. Rhyins, Photronics, Inc. (United States)
Patrick M. Martin, Photronics, Inc. (United States)

Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Alexander Starikov; Kenneth W. Tobin Jr., Editor(s)

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