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Proceedings Paper

Role of mask acuity in advanced lithographic process design
Author(s): Peter D. Buck
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Paper Abstract

Traditionally the design, layout, mask image and wafer image were considered to be equivalent. Effective modeling of the wafer image could be done with the assumption that the layout and mask had no impact on the predicted results. The ever-decreasing k1 factor and the associated increase of reticle enhancement technology (RET) has changed all this. Optical proximity correction (OPC) causes the layout to no longer look like either the design or the desired wafer image. The acuity constraints of mask lithography further complicate the problem by limiting the information transfer between the layout and the reticle image. Two design methodologies have evolved to deal with mask acuity limitations. One approach is to exhaustively characterize the mask and its relationship with wafer imaging through iterative empirical techniques. This is too time consuming in the process development phase and treats the mask process as a 'black box', but it does drive to a reasonable cost mask solution. The other is to require mask of the highest acuity, which most accurately replicate the layout. This approach is faster in the process design phase but locks in the highest mask costs for the entire process life cycle. Both approaches are inflexible with regard to alternate mask source, either from different mask litho tools and processes or from different mask vendors.

Paper Details

Date Published: 12 July 2002
PDF: 7 pages
Proc. SPIE 4692, Design, Process Integration, and Characterization for Microelectronics, (12 July 2002); doi: 10.1117/12.475682
Show Author Affiliations
Peter D. Buck, DuPont Photomasks, Inc. (United States)

Published in SPIE Proceedings Vol. 4692:
Design, Process Integration, and Characterization for Microelectronics
Alexander Starikov; Alexander Starikov; Kenneth W. Tobin Jr., Editor(s)

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