Share Email Print

Proceedings Paper

Packet scheduling for WDM fiber delay line buffers in photonic packet switches
Author(s): Takashi Yamaguchi; Ken-ichi Baba; Masayuki Murata; Ken-ichi Kitayama
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In this paper, we comparatively evaluate two photonic packet switch architectures with WDM-FDL buffers for synchronized variable length packets. The first one is an output buffer type switch, which stores packets in the FDL buffer attached to each output port. Another is a shared buffer type switch, which stores packets in the shared FDL buffer. The performance of a switch is greatly influenced by its architecture and the packet scheduling algorithm. We compare the performance of these two packet switches by applying different packet scheduling algorithms. Through simulation experiments, we show that each architecture has a parameter region for achieving a better performance. For the shared buffer type switch, we found that void space introduces unacceptable performance degradation when the traffic load is high. Accordingly, we propose a void space reduction method. Our simulation results show that our proposed method enables to the shared buffer type switch to outperform the output buffer type switch even under high traffic load conditions.

Paper Details

Date Published: 3 July 2002
PDF: 12 pages
Proc. SPIE 4874, OptiComm 2002: Optical Networking and Communications, (3 July 2002); doi: 10.1117/12.475303
Show Author Affiliations
Takashi Yamaguchi, Osaka Univ. (Japan)
Ken-ichi Baba, Osaka Univ. (Japan)
Masayuki Murata, Osaka Univ. (Japan)
Ken-ichi Kitayama, Osaka Univ. (Japan)

Published in SPIE Proceedings Vol. 4874:
OptiComm 2002: Optical Networking and Communications
Nasir Ghani; Krishna M. Sivalingam, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?