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Proceedings Paper

Patterning half-wavelength DRAM cell using chromelessp phase lithography (CPL)
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Paper Abstract

For each generation of DRAM cell layout design to achieve ever higher device density packing, tighter pitched array cell patterns are required. Very tight-pitched patterns present a great imaging challenge for sub-100nm devices. In order to pattern the cell patterns using KrF exposure, it is necessary to make use of resolution enhancement techniques (RET) such as phase shifting mask (PSM), off-axis illumination (OAI), and optical proximity correction (OPC). At k1 approximately 0.3 imaging, we have found a combination of PSM, OAI, and OPC that allows the most robust manufacturing process. In this paper, we have applied chromeless phase lithography (CPL) with OPC on the critical DRAM cell layers, such as capacitor node and contacts. The methodology of manipulating CPL image contrast by using phase cancelling effect is proposed. The mask design flow are discussed along with the consideration of data preparation and mask manufacturing complexity for CPL. The patterning performance has been characterized by using both simulation and experimental data from printed resist wafer. Using CPL mask with optimized OAI, a 0.8 NA 248nm exposure system is well capable of printing sub-100nm DRAM cell patterns.

Paper Details

Date Published: 30 July 2002
PDF: 13 pages
Proc. SPIE 4691, Optical Microlithography XV, (30 July 2002); doi: 10.1117/12.474629
Show Author Affiliations
Chungwei Michael Hsu, ASML MaskTools, Inc. (United States)
Ronfu Chu, Nanya Technology Corp. (Taiwan)
J. Fung Chen, ASML MaskTools, Inc. (United States)
Douglas J. Van Den Broeke, ASML MaskTools, Inc. (United States)
Xuelong Shi, ASML MaskTools, Inc. (United States)
Stephen Hsu, ASML MaskTools, Inc. (United States)
Troy Wang, Nanya Technology Corp. (Taiwan)

Published in SPIE Proceedings Vol. 4691:
Optical Microlithography XV
Anthony Yen, Editor(s)

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