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Proceedings Paper

New clear-out scheme to improve the overlay performance for a CMP process
Author(s): Yao-Wen Guo; Han-Pin Kao; Tsung-Chih Chien; Chiafu Chang; Hsin-Sung Lin; Yen-Fen Chen; Chin-Yu Ku
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Paper Abstract

To obtain good overlay performance, the quality of the wafer marks should be well designed. Although different brands of steppers and scanners use unique mark pattern design and alignment system, these exposure tools determine the position of marks through the signal obtaining from the height difference within the mark region. The largest problem of the marks is that the quality of the marks is influenced by the process conditions, such as film deposition, chemical mechanical polishing, and etching conditions, etc. In this work, we studied the impact of the CMP on the quality of the ASML alignment mark. The film structure and process flow are also investigated to understand the deformation of marks for different clear-out scheme. The lot-to-lot overlay variation can be prevented when the new clear-out scheme is employed.

Paper Details

Date Published: 16 July 2002
PDF: 8 pages
Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473432
Show Author Affiliations
Yao-Wen Guo, Vanguard International Semiconductor Corp. (Taiwan)
Han-Pin Kao, Vanguard International Semiconductor Corp. (Taiwan)
Tsung-Chih Chien, Vanguard International Semiconductor Corp. (Taiwan)
Chiafu Chang, Vanguard International Semiconductor Corp. (Taiwan)
Hsin-Sung Lin, Vanguard International Semiconductor Corp. (Taiwan)
Yen-Fen Chen, Vanguard International Semiconductor Corp. (Taiwan)
Chin-Yu Ku, Vanguard International Semiconductor Corp. (Taiwan)

Published in SPIE Proceedings Vol. 4689:
Metrology, Inspection, and Process Control for Microlithography XVI
Daniel J. C. Herr, Editor(s)

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