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Proceedings Paper

Nanotopography metrology for leading edge 300-mm process integration
Author(s): John Francis Valley; Todd Templeton; Chris L. Koliopoulos; Masanori Yoshise
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Paper Abstract

Wafer dimensional metrology, used to qualify substrates for lithography at the appropriate critical dimensions (CDs), historically reports shape and flatness. While these metrics have enabled several generations of educated wafer procurement, the high numerical aperture (NA) lithography required for sub-wavelength CDs now in production is becoming sensitive to front surface topography that is not reported by either shape or flatness. SEMI Standard M43, Guide for Reporting Wafer Nanotopography, is now published. According to this guide, 'Nanotopography is the non-planar deviation of the whole front wafer surface within a spatial wavelength range of approximately 0.2 to 20 mm and within the fixed quality area.' These nanometer scale non-planar deviations lead to within-die, die-to-die, and wafer-to- wafer variation that contributes to the overall focal budget. Several advanced CMOS device manufactures are no specifying incoming wafer nanotopography. These manufacturers all produce complex, high-speed, large die- size chips. In the following we detail wafer nanotopography metrology and nanotopography quantification. We also explore several known correlations of nanotopography to leading edge process integration issues.

Paper Details

Date Published: 16 July 2002
PDF: 10 pages
Proc. SPIE 4689, Metrology, Inspection, and Process Control for Microlithography XVI, (16 July 2002); doi: 10.1117/12.473431
Show Author Affiliations
John Francis Valley, ADE Phase Shift (United States)
Todd Templeton, ADE Phase Shift (United States)
Chris L. Koliopoulos, ADE Phase Shift (United States)
Masanori Yoshise, Japan ADE Ltd. (Japan)

Published in SPIE Proceedings Vol. 4689:
Metrology, Inspection, and Process Control for Microlithography XVI
Daniel J. C. Herr, Editor(s)

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