Share Email Print

Proceedings Paper

Circuit-level simulation approach to analyze system-level behavior of VCSEL-based optical interconnects
Author(s): Michiel De Wilde; Olivier Rits; Ronny Bockstaele; Jan M. Van Campenhout; Roel G. Baets
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

In order to satisfy the increasing demand for interchip interconnect bandwidth, a number of current research projects are concentrating on the use of waveguided optical interconnect arrays to span PCB-range distances. To accelerate system design and technology development, CAD tools for the design and the simulation of the interconnects are indispensable. We are developing a design methodology for optical inter-chip interconnects, to produce a tool for assisting system designers on deciding on product and parameter options for the different interconnect building blocks. A mandatory first step in this methodology development concerns the investigation of the combined impact of individual product and parameter variations on system-level interconnect system properties. Accurately predicting some interconnect properties requires analog simulation of the full electrical-optical-electrical links. Detailed models for the link building blocks involving geometrical calculations are much too slow for this purpose. Circuit-level simulation tools, with appropriate model descriptions, are much more suitable. In this paper, we describe our framework for the joint simulation of the entire optical interconnect with a mixed analog/digital system. We discuss in detail a number of issues that are involved with the implementation of circuit-level simulation models in the analog modelling language Verilog-AMS, and show a link simulation example.

Paper Details

Date Published: 15 April 2003
PDF: 11 pages
Proc. SPIE 4942, VCSELs and Optical Interconnects, (15 April 2003);
Show Author Affiliations
Michiel De Wilde, Univ. Gent (Belgium)
Olivier Rits, Univ. Gent (Belgium)
Ronny Bockstaele, Univ. Gent (Belgium)
Jan M. Van Campenhout, Univ. Gent (Belgium)
Roel G. Baets, Univ. Gent (Belgium)

Published in SPIE Proceedings Vol. 4942:
VCSELs and Optical Interconnects
Hugo Thienpont; Jan Danckaert, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?