This design case identifies generalizable features of a course-grained reconfigurable FPGA, Chameleon's reconfigurable platform. An FFT is used to identify typical design practices, problems, and solutions in targeting such a platform. This paper focuses on datapath mapping, separating it into functional design and placement of reconfigurable resources. In addition to exploring the design methodology, it analyzes numerical artifacts, demonstrates efficient packing of the data path, and highlights differences from ASIC design.

Date Published: 2 July 2002
PDF: 12 pages
Proc. SPIE 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV, (2 July 2002); doi: 10.1117/12.469748

Published in SPIE Proceedings Vol. 4867:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV
John Schewel; Philip B. James-Roxby; Herman H. Schmit; John T. McHenry, Editor(s)