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Proceedings Paper

Processing study of next-generation substrate
Author(s): Yung-Ming Chang; Chih-Hao Chou; Hung-Yi Lin; Tung-Chuan Wu; Thomas Hsieh
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Paper Abstract

Silicon on Insulator (SOI) technologies will play a major role for low-voltage, low-power device and MEMS in semiconductor developments. Today four main material technologies, BESOI, SIMOX, Smart Cut and ELO were developed but like BESOI substrate making process has simple steps and less equipment in vestment than others. This paper presents SOI wafer fabricated by direct heat-bonded method, thermally oxidizied Si wafer as handle layer and another prime Si wafer as device layer. By the ductile mode grinding and subsequent polishing methods to fabricate the desired device layer more than 10μm and quality of total thickness variation to be 3μm, roughness 5Å. Excellent quality of bonding SOI wafer with oxidation structure which act as etch stop or sacrificed layer at processes would be widely applied in MEMS, MOS, Optical Device and so on.

Paper Details

Date Published: 13 November 2002
PDF: 6 pages
Proc. SPIE 4934, Smart Materials II, (13 November 2002); doi: 10.1117/12.469186
Show Author Affiliations
Yung-Ming Chang, Industrial Technology Research Institute (Taiwan)
Chih-Hao Chou, Industrial Technology Research Institute (Taiwan)
Hung-Yi Lin, Industrial Technology Research Institute (Taiwan)
Tung-Chuan Wu, Industrial Technology Research Institute (Taiwan)
Thomas Hsieh, Kinik Precision Grinding Co. (Taiwan)

Published in SPIE Proceedings Vol. 4934:
Smart Materials II
Alan R. Wilson, Editor(s)

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