CMOS image sensors have several clear advantages over CCD image sensors: selective readout, low power, small size, high frame rate, on-chip functionality, and low cost. However CCD image system still dominates over digital camera market, because the CMOS image system has a poor dynamic range and peak signal-to-noise ratio. In this paper, we propose a new enhanced DR and SNR CMOS image sensor with pixel parallel analog-to-digital converter (ADC) and memory. The proposed reset and time-to-digital converter (TDC) increase the well capacity of the image sensor. Consequently, DR and peak SNR are increased simultaneously while other DR enhancement schemes can't increase peak SNR. The circuit reuse concept is proposed to increase the fill factor. We designed and simulated the proposed circuit and achieved 12bit resolution with 1000frames/sec. Power consumption per each pixel is 50nW. DR is increased by 36dB and peak SNR is enhanced by 18dB.

Date Published: 5 February 2003
PDF: 8 pages
Proc. SPIE 4796, Low-Light-Level and Real-Time Imaging Systems, Components, and Applications, (5 February 2003); doi: 10.1117/12.458064

Published in SPIE Proceedings Vol. 4796:
Low-Light-Level and Real-Time Imaging Systems, Components, and Applications
C. Bruce Johnson; Divyendu Sinha; Phillip A. Laplante, Editor(s)