Proceedings Paper
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Paper Abstract
The design of an ASIC, which is capable of connecting multiple Ethernets by SDH links through complex network topology, is given here. A closed-loop congestion control mechanism over the entire network is put forward, a scheduling algorithm for traffic of four differenct priorities is suggested and the requried buffer size under self-similar traffic is calculated.
Paper Details
Date Published: 25 October 2002
PDF: 6 pages
Proc. SPIE 4772, Electro-Optical System Design, Simulation, Testing, and Training, (25 October 2002); doi: 10.1117/12.456719
Published in SPIE Proceedings Vol. 4772:
Electro-Optical System Design, Simulation, Testing, and Training
Richard M. Wasserman; Scott L. DeVore, Editor(s)
PDF: 6 pages
Proc. SPIE 4772, Electro-Optical System Design, Simulation, Testing, and Training, (25 October 2002); doi: 10.1117/12.456719
Show Author Affiliations
Liqiao Han, Xi'an Jiaotong Univ. (China)
Published in SPIE Proceedings Vol. 4772:
Electro-Optical System Design, Simulation, Testing, and Training
Richard M. Wasserman; Scott L. DeVore, Editor(s)
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