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Proceedings Paper

Algorithms and architectures for implementing large-velocity filter banks
Author(s): Alan D. Stocker; Preben D. Jensen
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Paper Abstract

The velocity filter (or 3-D matched filter) is known to be a powerful signal processing technique for detecting and tracking weak moving objects in electro-optical image sequences. To date, however, its application has been limited by the enormous amounts of hardware required to implement the large 'filter banks' that are needed to cover the prior uncertainty in apparent target velocity. This paper presents the results of an algorithm and architecture study that explored ways of significantly reducing the real-time hardware required to obtain a specified level of performance with the velocity filter approach. The most effective solution, based on an optimum single-bit velocity filter implemented in a special-purpose bit serial processor, is capable of achieving extremely high filter computation rates on a single semi- custom VLSI chip. A real-time brassboard implementation of this architecture, the Velocity Filter Processor, is currently under development at Space Computer Corporation.

Paper Details

Date Published: 1 August 1991
PDF: 16 pages
Proc. SPIE 1481, Signal and Data Processing of Small Targets 1991, (1 August 1991); doi: 10.1117/12.45650
Show Author Affiliations
Alan D. Stocker, Space Computer Corp. (United States)
Preben D. Jensen, Space Computer Corp. (United States)

Published in SPIE Proceedings Vol. 1481:
Signal and Data Processing of Small Targets 1991
Oliver E. Drummond, Editor(s)

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