This paper describes an approach for optimizing hardware designs produced from software languages extended with constructs for parallel execution and hardware processing, such as the Handel-C language. Our aim is to optimize these programs by applying transformations that include the appropriate amount of parallelism, in order to obtain the best trade-offs in space and in time. These transformations can be applied automatically at compile time, enabling the programmer to adapt parallel programs rapidly to a specific hardware platform. Our transformational approach, which involves design sequentialisation and parallelisation, contains two novel features. First, we develop an algorithm for sequentialising parallel programs. This algorithm relaxes the scheduling of the original design, giving a scheduler the freedom to arrange it to achieve better results in speed, in size, or in both. Second, we combine this sequentialisation algorithm with pipeline vectorization, a technique known to reduce the execution delay of loops by pipelining the loop body. We adapt several transformation techniques used in vectorizing and parallelizing software compilers, such as loop unrolling and loop tiling, to widen the applicability of our method. Results show that our approach often works well: for instance a manually pipelined convolution design, for implementation in a Xilinx XC4000 device produced from a Handel-C description, is speeded up by over 2 times by our prototype compiler.

Date Published: 2 July 2002
PDF: 11 pages
Proc. SPIE 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV, (2 July 2002); doi: 10.1117/12.455467

Published in SPIE Proceedings Vol. 4867:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV
John Schewel; Philip B. James-Roxby; Herman H. Schmit; John T. McHenry, Editor(s)