Due to an increasing technology progress in the configurable hardware sector, which is currently dominated by FPGAs, new approaches like very fast re-configurable devices with ALU level granularity are on the rise. However, these coprocessor devices can not be programmed with conventional HW nor SW design approaches. To solve this dilemma, a combination is needed. This approach is described in this paper. Furthermore, an example how to program a re-configurable device is illustrated. This example consists of parts of an MPEG-4 decoder, which is running on the re-configurable processor platform XPP. The partitioning of these decoding algorithms into modules and the means of interaction between these modules is highlighted. In addition, the embedding of this algorithm in a XPP system is outlined.

Date Published: 2 July 2002
PDF: 12 pages
Proc. SPIE 4867, Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV, (2 July 2002); doi: 10.1117/12.455385

Published in SPIE Proceedings Vol. 4867:
Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications IV
John Schewel; Philip B. James-Roxby; Herman H. Schmit; John T. McHenry, Editor(s)