Share Email Print

Proceedings Paper

Update on focal-plane image processing research
Author(s): Sabrina E. Kemeny; Sayed I. Eid; Sunetra K. Mendis; Eric R. Fossum
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

An update on research activities at Columbia University in the area of focal-plane image processing is presented. Two thrust areas have been pursued: image reorganization for image compression and image half-toning. The image reorganization processor is an integration of a 256 X 256 frame-transfer CCD imager with CCD-based circuitry for pixel data reorganization to enable difference encoding for hierarchical image compression. The reorganization circuitry occupies 2 of the total chip area and is performed using three parallel-serial-parallel (SP3) registers, a pixel resequencing block, and a sampling block for differential output. The chip has achieved a CTE of 0.99994 in this new SP3 architecture, at an output rate of 83 X 103 pixels/sec. (0.9996 at 2 X 106 pixels/sec) and an overall output amplifier sensitivity of 3.2 (mu) V/electron. The half-toning chip design has been described previously, and consists of a 256 X 256 frame transfer imager, a pipeline register, and comparator circuit. Functional testing of these elements is reported at this time.

Paper Details

Date Published: 1 July 1991
PDF: 8 pages
Proc. SPIE 1447, Charge-Coupled Devices and Solid State Optical Sensors II, (1 July 1991); doi: 10.1117/12.45329
Show Author Affiliations
Sabrina E. Kemeny, Columbia Univ. (United States)
Sayed I. Eid, Columbia Univ. (United States)
Sunetra K. Mendis, Columbia Univ. (United States)
Eric R. Fossum, Columbia Univ. (United States)

Published in SPIE Proceedings Vol. 1447:
Charge-Coupled Devices and Solid State Optical Sensors II
Morley M. Blouke, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?