Proceedings Paper
Parametric time delay modeling for floating point units| Format | Member Price | Non-Member Price |
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Paper Abstract
A parametric time delay model to compare floating point unit implementations is proposed. This model is used to compare a previously proposed floating point adder using a redundant number representation with other high-performance implementations. The operand width, the fan-in of the logic gates and the radix of the redundant format are used as parameters to the model. The comparison is done over a range of operand widths, fan-in and radices to show the merits of each implementation.
Paper Details
Date Published: 6 December 2002
PDF: 8 pages
Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452014
Published in SPIE Proceedings Vol. 4791:
Advanced Signal Processing Algorithms, Architectures, and Implementations XII
Franklin T. Luk, Editor(s)
PDF: 8 pages
Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452014
Show Author Affiliations
Hossam A. H. Fahmy, Stanford Univ. (United States)
Albert A. Liddicoat, Stanford Univ. (United States)
Albert A. Liddicoat, Stanford Univ. (United States)
Michael J. Flynn, Stanford Univ. (United States)
Published in SPIE Proceedings Vol. 4791:
Advanced Signal Processing Algorithms, Architectures, and Implementations XII
Franklin T. Luk, Editor(s)
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