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Proceedings Paper

Design tradeoffs using truncated multipliers in FIR filter implementations
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Paper Abstract

This paper presents a general FIR filter architecture utilizing truncated tree multipliers for computation. The average error, maximum error, and variance of error due to truncation are derived for the proposed architecture. A novel technique that reduces the average error of the filter is presented, along with equations for computing the signal-to-noise ratio of the truncation error. A software tool written in Java is described that automatically generates structural VHDL models for specific filters based on this architecture, given parameters such as the number of taps, operand lengths, number of multipliers, and number of truncated columns. We show that a 22.5% reduction in area can be achieved for a 24-tap filter with 16-bit operands, 4 parallel multipliers, and 12 truncated columns. For this implementation, the average reduction error is only 9.18 × 10-5 ulps, and the reduction error SNR is only 2.4 dB less than the roundoff SNR of an equivalent filter without truncation.

Paper Details

Date Published: 6 December 2002
PDF: 12 pages
Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.452011
Show Author Affiliations
Eugene George Walters III, Lehigh Univ. (United States)
Michael J. Schulte, Lehigh Univ. (United States)

Published in SPIE Proceedings Vol. 4791:
Advanced Signal Processing Algorithms, Architectures, and Implementations XII
Franklin T. Luk, Editor(s)

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