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Proceedings Paper

Constant-delay MSB-first bit-serial adder
Author(s): Chang Yong Kang; Earl E. Swartzlander Jr.
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Paper Abstract

A new MSB-first bit-serial adder/subtracter architecture is proposed. The architecture utilizes a modified Manchester carry chain to accommodate the carry from the future LSB's. The carry chain is shown to have the constant delay of two AND gates and one XOR gate regardless of the operand width, which allows a fast constant operational clock frequency. When compared to the conventional parallel addition approach where the operand bits are stored and then added in parallel, the proposed architecture also provides a significant area saving. It is also shown that the proposed architecture can be generalized for radix-r operands.

Paper Details

Date Published: 6 December 2002
PDF: 6 pages
Proc. SPIE 4791, Advanced Signal Processing Algorithms, Architectures, and Implementations XII, (6 December 2002); doi: 10.1117/12.451778
Show Author Affiliations
Chang Yong Kang, Univ. of Texas/Austin (United States)
Earl E. Swartzlander Jr., Univ. of Texas/Austin (United States)

Published in SPIE Proceedings Vol. 4791:
Advanced Signal Processing Algorithms, Architectures, and Implementations XII
Franklin T. Luk, Editor(s)

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