Share Email Print

Proceedings Paper

Silicon CMOS-based vertical multimode interference optical taps
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

A compact, low loss, optical tap technology is critical for the incorporation of optical interconnects into mainstream CMOS processes. A recently introduced multimode interference effect based device has the potential for very high speed performance in a compact geometry and in a CMOS compatible process. For this work, 2-D and 3-D device simulations confirm a low excess optical loss on order of 0.1 dB, and a nominal 40% (2.2 dB) optical coupling into the CMOS circuitry over a wide range of guide to substrate distances. Simulated devices are on the order of 25micrometers in length and as narrow as 1 um. High temperature, hybrid polymer materials used for commercial CMOS inter-metal dielectric layers are targeted for tap fabrication and are incorporated into the models. Low cost, silicon CMOS based processing makes the new tap technology especially suitable for computer multi-chip module and board level interconnects, as well as for metro fiber to the home and desk telecommunications applications.

Paper Details

Date Published: 26 December 2001
PDF: 7 pages
Proc. SPIE 4435, Wave Optics and VLSI Photonic Devices for Information Processing, (26 December 2001); doi: 10.1117/12.451141
Show Author Affiliations
Vincent E. Stenger, Univ. of Cincinnati (United States)
Fred Richard Beyette Jr., Univ. of Cincinnati (United States)

Published in SPIE Proceedings Vol. 4435:
Wave Optics and VLSI Photonic Devices for Information Processing
Pierre Ambs; Fred Richard Beyette Jr.; Fred Richard Beyette Jr., Editor(s)

© SPIE. Terms of Use
Back to Top