Data structures that are carefully matched to the processing technology used to implement them can lead to cost-effective designs for radar signal classification/sorting devices. During the past decade, HRB Systems has developed several generations of devices for use in sorting radar signals. The older devices employed analog demodulators and complicated post- demodulation processing to generate a large feature vector containing a set of parameters describing each measured pulse. Clever use of algorithmic data structures specifically tailored to exploit the capabilities of VLSI ASIC fabrication technology eliminated the need for multipliers, making possible a digital demodulator that is much smaller, faster, more reliable, and less expensive than the analog versions. Little information is lost when much smaller feature vectors are used to describe the pulses, enabling further substantial reductions in the complexity of the post-demodulation processing. As a result, the new feature extractor has a price/performance ratio over a hundred times better than the older devices. A four-chip implementation of the new feature extractor is described.

Date Published: 1 August 1991
PDF: 7 pages
Proc. SPIE 1470, Data Structures and Target Classification, (1 August 1991); doi: 10.1117/12.44854

Published in SPIE Proceedings Vol. 1470:
Data Structures and Target Classification
Vibeke Libby, Editor(s)