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Proceedings Paper

Investigation of interlevel proximity effects case of the gate level over LOCOS
Author(s): Gilles Festes; Jean-Paul E. Chollet
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Paper Abstract

Reflected light from steps causes defects in photolithography: extra exposure from a reflective nonplanar substrate induces resist profile damage and CD variations. This phenomenon, called the interlevel proximity effect, is studied for the standard case of polysilicon gate level over LOCOS level (local oxidation on silicon). The problem is extended to a parametric study. For each parameter, we have obtained an interval of critical gate-LOCOS distances in which the patterns are seriously affected. To explain the evaluated results, a simple and appropriate theoretical model is proposed, based on the oblique propagation of light rays. Finally, from the experimental conclusions, solutions to reduce notching are presented.

Paper Details

Date Published: 1 July 1991
PDF: 11 pages
Proc. SPIE 1463, Optical/Laser Microlithography IV, (1 July 1991); doi: 10.1117/12.44785
Show Author Affiliations
Gilles Festes, France Telecom/CNET (France)
Jean-Paul E. Chollet, France Telecom/CNET (France)

Published in SPIE Proceedings Vol. 1463:
Optical/Laser Microlithography IV
Victor Pol, Editor(s)

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