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Proceedings Paper

Automated approach to the correlation of defect locations to electrical test results to determine yield reducing defects
Author(s): M. Michael Slama; Angela C. Patterson
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Paper Abstract

Automated defect detection using various techniques (including holography, digital image processing and particle detection) has provided process engineers with defect distributions and densities for all process levels. However, defect detection systems alone cannot differentiate between killer and nuisance defects, and can only give an indication of the potential yield reducing problems. The location of the defect with respect to the process level is important in determining the impact on the final device. Recent techniques have been developed to automatically separate killer defects from nuisance defects. This paper show how this technique is used to isolate the yield reducing defects. The method used shows how results from electrical test can be correlated with defect inspection results.

Paper Details

Date Published: 1 July 1991
PDF: 8 pages
Proc. SPIE 1464, Integrated Circuit Metrology, Inspection, and Process Control V, (1 July 1991); doi: 10.1117/12.44471
Show Author Affiliations
M. Michael Slama, National Semiconductor Corp. (United States)
Angela C. Patterson, Insystems (United States)

Published in SPIE Proceedings Vol. 1464:
Integrated Circuit Metrology, Inspection, and Process Control V
William H. Arnold, Editor(s)

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