Share Email Print

Proceedings Paper

Layout techniques for VLSI yield enhancement
Author(s): Zhan Chen; Lixin Zhang
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Advances in semiconductor technology allow the manufacture of VLSI circuits with millions of transistors. With the increase in chip size and the decrease in layout feature size, yield loss due to manufacturing defects has become a serious problem. To overcome this problem, various defect-tolerant techniques have been developed to reduce the design sensitivity to manufacturing defects. This paper reviews techniques for yield enhancement in compaction, routing, and floorplanning stages of layout design.

Paper Details

Date Published: 15 October 2001
PDF: 8 pages
Proc. SPIE 4600, Advances in Microelectronic Device Technology, (15 October 2001); doi: 10.1117/12.444666
Show Author Affiliations
Zhan Chen, Intel Corp. (United States)
Lixin Zhang, CSMC-HJ Corp. (China)

Published in SPIE Proceedings Vol. 4600:
Advances in Microelectronic Device Technology
Qin-Yi Tong; Ulrich M. Goesele, Editor(s)

© SPIE. Terms of Use
Back to Top