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Proceedings Paper

Design of a low-power 1.5-Gb/s CMOS 1:4 demultiplexer IC
Author(s): Wencai Lu; Zhigong Wang; Lei Tian; Tingting Xie; Yi Dong; Shizhong Xie
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Paper Abstract

A monolithic integrated photoreceiver for 1.55-micrometers wavelength fiber-optic receivers has been designed and fabricated with one amplifier stage, two stages of source follower and a feedback resistance structure. The optoelectronic integrated circuit (OEIC) receiver combines an InGaAs MSM photodetector with InP-based InA1As/InGaAs HEMT. The receiver demonstrates a transmitting bit rate of 2.5Gb/s with a transimpedance of 58(Omega) dB. While operating at 2.5Gbit/s, the chip consumes 160 MW at a single+5V supply voltage.

Paper Details

Date Published: 16 October 2001
PDF: 4 pages
Proc. SPIE 4603, Fiber Optics and Optoelectronics for Network Applications, (16 October 2001); doi: 10.1117/12.444554
Show Author Affiliations
Wencai Lu, Southeast Univ. (China)
Zhigong Wang, Southeast Univ. (China)
Lei Tian, Southeast Univ. (China)
Tingting Xie, Southeast Univ. (China)
Yi Dong, Tsinghua Univ. (China)
Shizhong Xie, Tsinghua Univ. (China)

Published in SPIE Proceedings Vol. 4603:
Fiber Optics and Optoelectronics for Network Applications
Jian Liu; Zhigong Wang, Editor(s)

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