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Proceedings Paper

Design and simulation of reusable IP for image convolution algorithm
Author(s): Jiannong N. Tong; Xuecheng Zou; Xubang Shen
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Paper Abstract

This paper proposes an IP hierarchy based on 3 X 3 convolution template to construct large-scale image convolution architecture, such as 6 X 6, 9 X 9 or more. It's an aid to speed up the designing for image- processing hardware system. The key hierarchies of 3 X 3 image convolution consist of parallel convolutions and pipelined multipliers. The hierarchies are designed for top- model with structural VHDL and all sub-models with RTL VHDL. The system is divided into some models and connected all after synthesized independently. Cadence and Synopsys are utilized for VHDL simulation and for synthesis respectively in order to obtain the preferable effects.

Paper Details

Date Published: 20 September 2001
PDF: 4 pages
Proc. SPIE 4552, Image Matching and Analysis, (20 September 2001); doi: 10.1117/12.441504
Show Author Affiliations
Jiannong N. Tong, Huazhong Univ. of Science and Technology (China)
Xuecheng Zou, Huazhong Univ. of Science and Technology (China)
Xubang Shen, Huazhong Univ. of Science and Technology (China)

Published in SPIE Proceedings Vol. 4552:
Image Matching and Analysis
Bir Bhanu; Jun Shen; Tianxu Zhang, Editor(s)

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