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Proceedings Paper

In-line defect to final test bitmap correlations: a Bayesian approach
Author(s): Mark A. Spinelli; K. Preston White
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Paper Abstract

Physical failure analysis on inspected and bitmapped wafers prove a compelling way to pareto defect sources on memory products. Failure analysis also indicates the relationship between the electrical signature (row, column etc.) and the physical layer (gate, metal-0, etc.) Failure analysis very rarely, however, shows a one-to-one relationship between defects and electrical signatures. Electrical signatures can correspond to different defect sources: a double-bit failure might indicate either a blocked common-source contact or cell- to-cell leakage. Likewise, foreign material at the gate level might cause a cross failure if shorted to a contact, or a row failure if shorted to another gate. Yield engineers have developed algorithms to quantify the relationship between inline defects and electrical signatures; commercially available semiconductor-specific software can do the same. Although varying in their capability, these tools answer following questions: given that a die has a particular electrical signature, what is the most likely source of the defect? And given that a die has a defect at a certain level, what electrical signature will this most likely cause? Bayes' theorem can provide an answer to both. We apply Bayes' theorem to show the relationship between a sample of physical defects and electrical signatures on a DRAM product.

Paper Details

Date Published: 23 April 2001
PDF: 9 pages
Proc. SPIE 4406, In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II, (23 April 2001);
Show Author Affiliations
Mark A. Spinelli, Dominion Semiconductor LLC (United States)
K. Preston White, Univ. of Virginia (United States)


Published in SPIE Proceedings Vol. 4406:
In-Line Characterization, Yield, Reliability, and Failure Analysis in Microelectronic Manufacturing II
Gudrun Kissinger; Larg H. Weiland, Editor(s)

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