Share Email Print

Proceedings Paper

Lithography aspects of dual-damascene interconnect technology
Author(s): Mireille Maenhoudt; Diziana Van Goidsenhoven; Ivan K.A. Pollentier; Kurt G. Ronse; Muriel Lepage; Herbert Struyf; Marleen Van Hove
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The introduction of Cu and low-k dielectrics in back-end-of- line processes has serious implications for lithography. Different low-k material shave different reflective properties and also the potential use of hard masks has consequences for lithography. Furthermore, depending on the integration scheme that is chosen, various issues for lithography and etch are showing up. While the first photo step is on a planar substrate, the second photo has to cover a topography. This can have large implications on CD uniformity and the amount of material left for the subsequent etch.

Paper Details

Date Published: 26 April 2001
PDF: 13 pages
Proc. SPIE 4404, Lithography for Semiconductor Manufacturing II, (26 April 2001); doi: 10.1117/12.425203
Show Author Affiliations
Mireille Maenhoudt, IMEC (Belgium)
Diziana Van Goidsenhoven, IMEC (Belgium)
Ivan K.A. Pollentier, IMEC (Belgium)
Kurt G. Ronse, IMEC (Belgium)
Muriel Lepage, IMEC (Belgium)
Herbert Struyf, IMEC (Belgium)
Marleen Van Hove, IMEC (Belgium)

Published in SPIE Proceedings Vol. 4404:
Lithography for Semiconductor Manufacturing II
Chris A. Mack; Tom Stevenson, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?