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Proceedings Paper

VASP-4096: a very high performance programmable device for digital media processing applications
Author(s): Argy Krikelis
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Paper Abstract

Over the past few years, technology drivers for microprocessors have changed significantly. Media data delivery and processing--such as telecommunications, networking, video processing, speech recognition and 3D graphics--is increasing in importance and will soon dominate the processing cycles consumed in computer-based systems. This paper presents the architecture of the VASP-4096 processor. VASP-4096 provides high media performance with low energy consumption by integrating associative SIMD parallel processing with embedded microprocessor technology. The major innovations in the VASP-4096 is the integration of thousands of processing units in a single chip that are capable of support software programmable high-performance mathematical functions as well as abstract data processing. In addition to 4096 processing units, VASP-4096 integrates on a single chip a RISC controller that is an implementation of the SPARC architecture, 128 Kbytes of Data Memory, and I/O interfaces. The SIMD processing in VASP-4096 implements the ASProCore architecture, which is a proprietary implementation of SIMD processing, operates at 266 MHz with program instructions issued by the RISC controller. The device also integrates a 64-bit synchronous main memory interface operating at 133 MHz (double-data rate), and a 64- bit 66 MHz PCI interface. VASP-4096, compared with other processors architectures that support media processing, offers true performance scalability, support for deterministic and non-deterministic data processing on a single device, and software programmability that can be re- used in future chip generations.

Paper Details

Date Published: 29 March 2001
PDF: 7 pages
Proc. SPIE 4313, Media Processors 2001, (29 March 2001); doi: 10.1117/12.420802
Show Author Affiliations
Argy Krikelis, Aspex Technology Ltd. (United Kingdom)

Published in SPIE Proceedings Vol. 4313:
Media Processors 2001
Sethuraman Panchanathan; V. Michael Bove Jr.; Subramania I. Sudharsanan, Editor(s)

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