A dual polysilicon gate structure is required to increase the circuit speed and the packing density, as well as the low-power operation as the design rule of CMOS scales down to sub- 0.25micrometers . In order to get the superior device performance of 0.18micrometers logic device, we need to do the gate implantation prior to polysilicon etch. The critical dimensions (CD) different between NMOS and PMOS during polysilicon gate etching needs to be reduced for matching the design drive current of NMOS and PMOS. In this work, the pressure, the bias power, the total flow of CF₄ and Cl₂ and the N₂ flow are used for the investigation of 0.18micrometers device during the dual gate etch. After optimizing all etch parameters, the CD offset is small between NMOS and PMOS. The vertical profile, the small bias, and CD micro-loading are obtained using in-situ BARC and polysilicon etching. The result of pitting free, stringers free and notching free after dual polysilicon etching is achieved, and the remaining thickness of deep UV photoresist at shoulder is about 800-880A. From this study, both good performance device and the process controllability are obtained with in-situ bottom anti- reflective coating and dual polysilicon gate etching.

Date Published: 23 August 2000
PDF: 12 pages
Proc. SPIE 4182, Process Control and Diagnostics, (23 August 2000); doi: 10.1117/12.410091

Published in SPIE Proceedings Vol. 4182:
Process Control and Diagnostics
Michael L. Miller; Kaihan A. Ashtiani, Editor(s)