Bandwidth incompatibility between a central processing unit (CPU) and printed circuit board (PCB) within a computer system has been a long noted problem. Physics and material sciences suggest that the problem could become worse before getting solved. This is fundamentally due to nature of propagation of electric signals in very large scale integration of conductive wires. The market has witnessed a rapid increase in chip level clock frequency (for a mainstream PC) from 100 MHz few years ago to 800 MHz nowadays. The PC bus bandwidth, however, for the same time span, grew only from 33 MHz to 100 MHz. Although the widely anticipated adoption of 133 MHz is on its way, any serious technical challenges remain. Such a large magnitude of bandwidth discrepancy between the chip and board levels has prompted Intel Corp. to aggressively invest into various technologies to increase speed at board level so that the performance of its future generation of faster and more powerful CPU chips can be effectively utilized. Rambus, Inc. with a strong backing from Intel has come up with a faster memory bus technology that can increase the bus speed several times. Competitions from sampling a data bus at both clock signal edges using the so-called double data rate (DDR) technology are also making their strides. However, high-speed electric signals in densely packed conductive wiring structures inevitably generate the so-called electromagnetic interference among each others. Tougher challenges lie ahead for future generations of large bandwidth interconnect technology at the board level.

Date Published: 17 November 2000
PDF: 6 pages
Proc. SPIE 4109, Critical Technologies for the Future of Computing, (17 November 2000); doi: 10.1117/12.409223

Published in SPIE Proceedings Vol. 4109:
Critical Technologies for the Future of Computing
Sunny Bains; Leo J. Irakliotis, Editor(s)