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Proceedings Paper

Analysis of serious bit-line failure on 0.19-um 64M DRAM with STI technology
Author(s): Chung Lee; Chih-Tung Tang
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Paper Abstract

When 0.19um 64M DRAM was been developing that suffered very serious bit line failure. Because it is the first product with shallow trench isolation (STI) technology in VIS, obviously some previous FA experiences in LOCOS is not applicable to this case. After took much effort, finally, cross section/plane view TEM and Wright etching analysis shown there were two root causes. 1) Stress induced dislocation in silicon is the major problem witch always occurs at special layout and induced most of the bit line fail (especially long bit line fail). 2) Poly plug residue from improper IPO1 CMP induced bit line fail.

Paper Details

Date Published: 23 October 2000
PDF: 11 pages
Proc. SPIE 4229, Microelectronic Yield, Reliability, and Advanced Packaging, (23 October 2000); doi: 10.1117/12.404865
Show Author Affiliations
Chung Lee, Taiwan Semiconductor Manufacturing Co. (Taiwan)
Chih-Tung Tang, Winbond (Taiwan)

Published in SPIE Proceedings Vol. 4229:
Microelectronic Yield, Reliability, and Advanced Packaging
Cher Ming Tan; Yeng-Kaung Peng; Mali Mahalingam; Krishnamachar Prasad, Editor(s)

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