Share Email Print
cover

Proceedings Paper

Hardware-based image processing library for Virtex FPGA
Author(s): Marek Gorgon; Ryszard Tadeusiewicz
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

The paper considers hardware-based realization of image processing algorithms. Usage of single FPGA device - Virtex as a processing element capable to carry out image processing in real-time is thoroughly discussed. For implementation of the algorithms in hardware resources specialized IP cores architectures has been designed and tested. The image-processing library consists of individual cores able to be linked together on a software level and implemented in high capacity FPGA devices is proposed.

Paper Details

Date Published: 6 October 2000
PDF: 10 pages
Proc. SPIE 4212, Reconfigurable Technology: FPGAs for Computing and Applications II, (6 October 2000); doi: 10.1117/12.402510
Show Author Affiliations
Marek Gorgon, Univ. of Mining and Metallurgy (Poland)
Ryszard Tadeusiewicz, Univ. of Mining and Metallurgy (Poland)


Published in SPIE Proceedings Vol. 4212:
Reconfigurable Technology: FPGAs for Computing and Applications II
John Schewel; Peter M. Athanas; Chris H. Dick; John T. McHenry, Editor(s)

© SPIE. Terms of Use
Back to Top
PREMIUM CONTENT
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?
close_icon_gray