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Proceedings Paper

High-performance vs. low-power technology roadmaps: how are they different?
Author(s): Dirk Wristers
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Paper Abstract

The effectiveness of a platform development approach for next general logic technologies is discussed. Of the critical material changes that are being considered for the 0.1 micrometers technology generation and beyond, high k gate dielectrics will be driven by low power technology needs while low k and SOI technology enhancements will be driven by high performance technology requirements along with other technology 'extras'. The result is less overlap in technology requirements for low power logic technology relative to high performance logic technology at the immediate technology generation in question, but increased early learning for the following generation.

Paper Details

Date Published: 18 August 2000
PDF: 6 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395722
Show Author Affiliations
Dirk Wristers, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

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