Share Email Print

Proceedings Paper

Investigations on the impacts of misalignment in the integration of 0.18-u multilevel interconnect
Author(s): Teck Jung Tang; Juan Boon Tan; Sajan R. Marokkey; Tae Jong Lee; Alan Cuthbertson
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

As technology continues to shrink with tighter design rules, it becomes inevitable for the integrated process to demand a more stringent control over the in-line parameters. For multilevel interconnect, each processing step in the formation of every layer of via plug and metal interconnect impacts the overall performance and yield of the silicon wafer. The control of the process thus becomes even more challenging as more layers of interconnect are required to meet the speed performance and density requirements.

Paper Details

Date Published: 18 August 2000
PDF: 8 pages
Proc. SPIE 4181, Challenges in Process Integration and Device Technology, (18 August 2000); doi: 10.1117/12.395716
Show Author Affiliations
Teck Jung Tang, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Juan Boon Tan, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Sajan R. Marokkey, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Tae Jong Lee, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Alan Cuthbertson, Chartered Semiconductor Manufacturing, Ltd. (United States)

Published in SPIE Proceedings Vol. 4181:
Challenges in Process Integration and Device Technology
David Burnett; Shin'ichiro Kimura; Bhanwar Singh, Editor(s)

© SPIE. Terms of Use
Back to Top