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Proceedings Paper

Wafer-level surface-mountable chip size packaging for MEMS and ICs
Author(s): Stephane Renard
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Paper Abstract

TRONIC'S Microsystems has developed in collaboration with LETI and ELA Recherche a Chip Size Packaging for MEMS and ICs using standard MST technologies and batch wafer processing. It allows to integrate on a single package the Electro-Mechanical Structure of the circuits, the connections and the encapsulation. After dicing, the device which is a package of its own can be easily handled and directly mounted on a circuit board. The connection pads allows the mounting on a board using standard Surface Mounting Technologies and the reworkability.

Paper Details

Date Published: 15 August 2000
PDF: 6 pages
Proc. SPIE 4176, Micromachined Devices and Components VI, (15 August 2000); doi: 10.1117/12.395635
Show Author Affiliations
Stephane Renard, TRONIC'S Microsystems (France)

Published in SPIE Proceedings Vol. 4176:
Micromachined Devices and Components VI
Eric Peeters; Oliver Paul, Editor(s)

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