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Proceedings Paper

Random line selected charge accumulation (RLCA) CCD readout structure for high-frame-rate infrared image application
Author(s): Gwo-Ji Horng; Chun-Yen Chang; Yung Chau Yen; Weng-Lyang Wang
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Paper Abstract

A 512 X 512 monolithic Platinum Silicide Schottky Barrier detector array with random line selectable operation was proposed. The device modified from an interline CCD configuration by adapt a Random Line selected Charge Accumulation charge-coupled device on the vertical register and four tap readout on the horizontal CCD register to achieve a high frame rate and high fill factor operation. A 9-bit digital decoder is used to select which line of the sensor array that transfer their signals to the vertical CCD register. Accompanied with the vertical reset drain circuitry, either one line or up to 512 lines of the video signals can be selected and transferred to the vertical CCD register. All of the video signals on the unselected lines are then transferred to the vertical CCD channel simultaneously and finally dumped to the vertical reset drain. Since this unique readout structure, a frame rate of up to 240 frames/second can be achieved for 128 X 128 of the SBD array under 5 MHz of clock frequency. A high-speed sub-frame readout format can be easily fulfilled under this architecture. This architecture not only maintains the advantages of line-addressed charge- accumulation structure but also provides the capability to readout any portion of the array.

Paper Details

Date Published: 17 July 2000
PDF: 9 pages
Proc. SPIE 4028, Infrared Detectors and Focal Plane Arrays VI, (17 July 2000); doi: 10.1117/12.391728
Show Author Affiliations
Gwo-Ji Horng, National Chiao Tung Univ. (Taiwan)
Chun-Yen Chang, National Chiao Tung Univ. (Taiwan)
Yung Chau Yen, CMOS Sensor Inc. (United States)
Weng-Lyang Wang, CMOS Sensor Inc. (United States)

Published in SPIE Proceedings Vol. 4028:
Infrared Detectors and Focal Plane Arrays VI
Eustace L. Dereniak; Robert E. Sampson, Editor(s)

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