Proceedings Paper
Determining and reducing the overhead losses in an ASIC-type environment| Format | Member Price | Non-Member Price |
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Paper Abstract
With the reduce cycle times required to produce customized chips to the end user, the inherent overhead time that is involved with running small lots or even send ahead wafers need to be minimized and optimized to provide reasonable levels of raw throughput. By understanding the process, from the completion of one lot to the start of the next, measurements and actions can be undertaken to outline improvements in the process.
Paper Details
Date Published: 5 July 2000
PDF: 4 pages
Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); doi: 10.1117/12.389085
Published in SPIE Proceedings Vol. 4000:
Optical Microlithography XIII
Christopher J. Progler, Editor(s)
PDF: 4 pages
Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); doi: 10.1117/12.389085
Show Author Affiliations
Dennis B. Ames, IBM Microelectronics Div. (United States)
Published in SPIE Proceedings Vol. 4000:
Optical Microlithography XIII
Christopher J. Progler, Editor(s)
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