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Proceedings Paper

Electrical critical dimension metrology for 100-nm linewidths and below
Author(s): Andrew Grenville; Brian Coombs; John M. Hutchinson; Kelin J. Kuhn; David Miller; Patrick M. Troccolo
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Paper Abstract

In this paper, we have demonstrated an electrical CD process capable of resolving linewidth swell below 100 nm compatible with a standard polysilicon patterning flow. Appropriate selection of dopant species combined with a reduction in anneal temperature were in the primary means for achieving a physical to electrical linewidth bias of 20 nm. These findings supported our hypothesis that dopant our-diffusion was the primary source of the bias. Also, ECD metrology is applied to quantifying poly CD variations in the presence of substrate topography.

Paper Details

Date Published: 5 July 2000
PDF: 8 pages
Proc. SPIE 4000, Optical Microlithography XIII, (5 July 2000); doi: 10.1117/12.389034
Show Author Affiliations
Andrew Grenville, Intel Corp. (United States)
Brian Coombs, Intel Corp. (United States)
John M. Hutchinson, Intel Corp. (United States)
Kelin J. Kuhn, Intel Corp. (United States)
David Miller, Intel Corp. (United States)
Patrick M. Troccolo, Intel Corp. (United States)

Published in SPIE Proceedings Vol. 4000:
Optical Microlithography XIII
Christopher J. Progler, Editor(s)

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