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Proceedings Paper

Metric for process optimization on substrates with transparent stacks in optical lithography
Author(s): Brian Martin; Graham G. Arthur
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Paper Abstract

A new metric for set-up of resist processes on transparent films is described using CMOS active area layer as a test vehicle for lithography simulations. Results show that the metric Es/Ec, where Es is exposure to size and Ec exposure to clear a high resolution feature, is more useful than the conventional ratio Es/Eo and where Eo is exposure to clear an open field area. High values of Es/Ec can protect against resist scumming if film thicknesses are chosen correctly, but if not accounted for at the sub-half-micron scale can be as low as 1.1. Where film thicknesses predict low Es/Ec, the ratio can be increased by use of bottom ARC.

Paper Details

Date Published: 2 June 2000
PDF: 7 pages
Proc. SPIE 3998, Metrology, Inspection, and Process Control for Microlithography XIV, (2 June 2000); doi: 10.1117/12.386517
Show Author Affiliations
Brian Martin, Mitel Semiconductor (United Kingdom)
Graham G. Arthur, Rutherford Appleton Lab. (United Kingdom)

Published in SPIE Proceedings Vol. 3998:
Metrology, Inspection, and Process Control for Microlithography XIV
Neal T. Sullivan, Editor(s)

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