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Proceedings Paper

Simultaneous multithreaded processor enhanced for multimedia applications
Author(s): Friederich Mombers; Michel Thomas
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Paper Abstract

The paper proposes a new media processor architecture specifically designed to handle state-of-the-art multimedia encoding and decoding tasks. To achieve this, the architecture efficiently exploit Data-, Instruction- and Thread-Level parallelisms while continuously adapting its computational resources to reach the most appropriate parallelism level among all the concurrent encoding/decoding processes. Looking at the implementation constraints, several critical choices were adopted that solve the interconnection delay problem, lower the cache misses and pipeline stalls effects and reduce register files and memory size by adopting a clustered Simultaneous Multithreaded Architecture. We enhanced the classic model to exploit both Instruction and Data Level Parallelism through vector instructions. The vector extension is well justified for multimedia workload and improves code density, crossbars complexity, register file ports and decoding logic area while it still provides an efficient way to fully exploit a large set of functional units. An MPEG-2 encoding algorithms based on Hybrid Genetic search has been implemented that show the efficiency of the architecture to adapt its resources allocation to better fulfill the application requirements.

Paper Details

Date Published: 29 December 1999
PDF: 12 pages
Proc. SPIE 3970, Media Processors 2000, (29 December 1999); doi: 10.1117/12.375232
Show Author Affiliations
Friederich Mombers, Swiss Federal Institute of Technology/Laussane (Switzerland)
Michel Thomas, Swiss Federal Institute of Technology/Lausanne (Switzerland)

Published in SPIE Proceedings Vol. 3970:
Media Processors 2000
Sethuraman Panchanathan; V. Michael Bove Jr.; Subramania I. Sudharsanan, Editor(s)

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