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Proceedings Paper

Fully parallel fuzzy logic processor architecture: exceeding one billion rules per second
Author(s): Michael Lees; Duncan Campbell
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Paper Abstract

A novel, very high-performance fuzzy logic processor architecture has been developed and conceptually proven. Processing of over 1.2 billion fuzzy logic instructions per second is possible. It is an 8-bit, fully parallel, synchronous, pipelined employing max-min based rule inferencing. The concept has been proven using complex programmable logic devices (CPLDs), exploiting both the high gate count and I/O pin count, as well as the reconfigurable structure. True non-singleton center-of-gravity defuzzification has also been developed incorporating an optimized dividing speeds significantly greater than the currently available commercial deices. Implementation in CPLDs allows reconfigurability in the fuzzy logic design, while custom devices allow a much greater degree of integration and potential for even greater processing speeds. High speed fuzzy logic processing is particularly suited to high bandwidth data processing applications such as virtual reality.

Paper Details

Date Published: 8 October 1999
PDF: 11 pages
Proc. SPIE 3893, Design, Characterization, and Packaging for MEMS and Microelectronics, (8 October 1999); doi: 10.1117/12.368442
Show Author Affiliations
Michael Lees, La Trobe Univ. (Australia)
Duncan Campbell, La Trobe Univ. (Australia)

Published in SPIE Proceedings Vol. 3893:
Design, Characterization, and Packaging for MEMS and Microelectronics
Bernard Courtois; Serge N. Demidenko, Editor(s)

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