Share Email Print

Proceedings Paper

Integrated yield and CD enhancement for advanced DUV lithography
Author(s): Murthy S. Krishna; Emir Gurer; Tom X. Zhong; Ed C. Lee; John W. Salois; Reese M. Reynolds
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

Defect reduction and yield enhancements are increasingly critical for advanced DUV lithography used in semiconductor manufacturing. The key to achieving defect reduction and maximizing yield is to focus on the developer module of the Track where the majority of defects are created. For optimum defect reduction, the rinse nozzle should provide good liquid distribution, uniform coverage of wafer, excellent rinsing action and low impact on wafer. The developer catch cup chamber should provide an uniform air velocity field to reduce turbulence, backflow and recirculation. An optimized process to leverage maximum benefit from rinse nozzle and catch cup chamber is also required. A solution to meet these requirements is presented here. This approach resulted in reducing defect counts by a factor of two along with a simultaneous reduction in develop process time by 23% and wider process latitude. In the advanced DUV 248 nm era, for 130 - 180 nm geometries using extremely sensitive and high contrast resists, understanding and minimizing the contribution of the developer process to CD control is very critical. The key components to improve CD control are enhanced developer nozzle in conjunction with develop process optimization. The developer nozzle should provide uniform coverage and result in low impact on wafer. This enables significant CD uniformity improvement without compromising defect reduction and yield enhancement. An all low impact chemical delivery (rinse and develop) system was designed to eliminate pattern collapse of 180 - 130 nm features. A solution to meet these requirements is presented here. The develop rate uniformity was improved by 30% for both Acetal- based type A resist and ESCAP-based type B resist. CD uniformity was improved by 25% for type A resist. The uniqueness of this project is an integrated and synergistic approach to yield and CD control for advanced DUV lithography, to maximize semiconductor-manufacturing productivity.

Paper Details

Date Published: 27 August 1999
PDF: 9 pages
Proc. SPIE 3884, In-Line Methods and Monitors for Process and Yield Improvement, (27 August 1999); doi: 10.1117/12.361360
Show Author Affiliations
Murthy S. Krishna, Silicon Valley Group, Inc. (United States)
Emir Gurer, Silicon Valley Group, Inc. (United States)
Tom X. Zhong, Silicon Valley Group, Inc. (United States)
Ed C. Lee, Silicon Valley Group, Inc. (United States)
John W. Salois, Silicon Valley Group, Inc. (United States)
Reese M. Reynolds, Silicon Valley Group, Inc. (United States)

Published in SPIE Proceedings Vol. 3884:
In-Line Methods and Monitors for Process and Yield Improvement
Sergio A. Ajuria; Jerome F. Jakubczak, Editor(s)

© SPIE. Terms of Use
Back to Top
Sign in to read the full article
Create a free SPIE account to get access to
premium articles and original research
Forgot your username?