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Proceedings Paper

Polysilicon planarization and plug recess etching in a decoupled plasma source chamber using two endpoint techniques
Author(s): George A. Kaplita; Stefan Schmitz; Rajiv Ranade; Gangadhara S. Mathad
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Paper Abstract

The planarization and recessing of polysilicon to form a plug are processes of increasing importance in silicon IC fabrication. While this technology has been developed and applied to DRAM technology using Trench Storage Capacitors, the need for such processes in other IC applications (i.e. polysilicon studs) has increased. Both planarization and recess processes usually have stringent requirements on etch rate, recess uniformity, and selectivity to underlying films. Additionally, both processes generally must be isotropic, yet must not expand any seams that might be present in the polysilicon fill. These processes should also be insensitive to changes in exposed silicon area (pattern factor) on the wafer. A SF6 plasma process in a polysilicon DPS (Decoupled Plasma Source) reactor has demonstrated the capability of achieving the above process requirements for both planarization and recess etch. The SF6 process in the decoupled plasma source reactor exhibited less sensitivity to pattern factor than in other types of reactors. Control of these planarization and recess processes requires two endpoint systems to work sequentially in the same recipe: one for monitoring the endpoint when blanket polysilicon (100% Si loading) is being planarized and one for monitoring the recess depth while the plug is being recessed (less than 10% Si loading). The planarization process employs an optical emission endpoint system (OES). An interferometric endpoint system (IEP), capable of monitoring lateral interference, is used for determining the recess depth. The ability of using either or both systems is required to make these plug processes manufacturable. Measuring the recess depth resulting from the recess process can be difficult, costly and time- consuming. An Atomic Force Microscope (AFM) can greatly alleviate these problems and can serve as a critical tool in the development of recess processes.

Paper Details

Date Published: 3 September 1999
PDF: 8 pages
Proc. SPIE 3882, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing V, (3 September 1999); doi: 10.1117/12.361328
Show Author Affiliations
George A. Kaplita, IBM Corp. (United States)
Stefan Schmitz, IBM Corp. (United States)
Rajiv Ranade, Infineon Corp. (United States)
Gangadhara S. Mathad, Infineon Corp. (United States)

Published in SPIE Proceedings Vol. 3882:
Process, Equipment, and Materials Control in Integrated Circuit Manufacturing V
Anthony J. Toprac; Kim Dang, Editor(s)

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