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Proceedings Paper

Polysilicon gate functional failure mechanism
Author(s): Judith B. Barker
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Paper Abstract

One of the most widespread uses of polysilicon in MOS devices is as the gate electrode for transistors. The gates described in this paper were processed via a two-stage polysilicon deposition. The first deposition stage grew a thin gate polysilicon, which was used as a screen for transistor threshold adjust implants. This was followed by a thick gate polysilicon deposition. All polysilicon depositions described in this paper were deposited in a vertical furnace. It was observed that production wafers in the top position of the polysilicon furnace and directly under dummy wafers displayed unusually high failure frequencies, called functional failures. This is a general failure mode, usually associated with defectivity. Similarities were noted between this failure mode and another failure mode for QBD (charge to breakdown of gate oxide). Both failure modes occurred whenever the production wafers were loaded directly underneath dummy wafers at the thin polysilicon deposition. Atomic Force Microscopy or AFM was used to measure the surface roughness and maximum peak-to-valley height on test wafers that mimicked production wafers. The surface roughness and peak-to-valley measurements were greatest at the top positions of the polysilicon furnace, indicating rougher polysilicon. By removing the dummy wafer directly above the top production wafer, it was found that the production wafers had smoother polysilicon growth. In this paper a mechanism for these functional failures is described that explains the relationship between functional failures and wafer position in the polysilicon furnace. It is demonstrated that when a product wafer is placed under a dummy wafer more silane reacts on the dummy wafer surface than on the production wafer. This is evidenced by the larger RMS surface roughness on the production wafer, as measured by AFM. Production wafers with polysilicon deposited at positions away from dummy wafers had lower RMS surface roughness. During subsequent HF treatments, the HF etched the valleys and underlying gate oxide, which produced oxide pinholes and caused the functional failures.

Paper Details

Date Published: 3 September 1999
PDF: 8 pages
Proc. SPIE 3882, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing V, (3 September 1999); doi: 10.1117/12.361308
Show Author Affiliations
Judith B. Barker, Motorola (United States)

Published in SPIE Proceedings Vol. 3882:
Process, Equipment, and Materials Control in Integrated Circuit Manufacturing V
Anthony J. Toprac; Kim Dang, Editor(s)

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