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Proceedings Paper

Defect reduction methodologies for damascene interconnect process development
Author(s): Andrew Skumanich; Man-Ping Cai
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Paper Abstract

A critical aspect of interconnect process development is identifying and eliminating yield impacting defects. A methodology is described which has been implemented at Applied Materials to utilize wafer metrology tools to drive process development for advanced interconnect fabrication. The methodology is based on a patterned wafer inspection tool, the WF736Duo, combined with a high throughput defect- review SEM with automatic defect classification, the SEMVision. This combination is tools facilitates defect sourcing and elimination. The requirements for defect reduction are increased since defects can result from both the levels and the interaction between levels. A full-flow Cu damascene interconnect process is examined from oxide deposition to final electrical test to establish inspection strategies for defect reduction. The inspection points for optimal defect reduction are identified based on e-test determination of yield limiting defects. The WF736 was utilized to capture a wide range of defects at the various processing steps. The progression of the defects is tracked to the final e-test point. This tracking both establishes the key defect types and facilitates defect sourcing. Further, the unique ability of the WF736 to segregate defects during the inspection with no loss in throughput, along with the SEMVision ADC analysis, allowed for faster defect sourcing.

Paper Details

Date Published: 11 August 1999
PDF: 10 pages
Proc. SPIE 3883, Multilevel Interconnect Technology III, (11 August 1999); doi: 10.1117/12.360575
Show Author Affiliations
Andrew Skumanich, Applied Materials Inc. (United States)
Man-Ping Cai, Applied Materials Inc. (United States)

Published in SPIE Proceedings Vol. 3883:
Multilevel Interconnect Technology III
Mart Graef; Divyesh N. Patel, Editor(s)

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